Generally, a transistor of a metal-oxide-semiconductor (MOS) structure includes a gate electrode (hereinafter, referred to as “gate line”) formed in a line shape on a semiconductor substrate such as a silicon substrate, and source/drain regions formed by doping portions of the semiconductor substrate that are exposed at both sides of the gate line with n-type or p-type impurities. A linewidth of the gate electrode is determined according to a design rule. As semiconductor devices become highly integrated, the linewidth of the gate electrode reduces.
According to a method of manufacturing a gate line contact of a semiconductor device of a prior art, a device isolation layer is formed on a silicon substrate by a shallow trench isolation (STI) process to isolate an active region from an inactive region. Next, a plurality of gate lines are formed on the substrate, and a spacer formed of an insulating material (for example, a silicon nitride layer) is formed on both sidewalls of the gate line. Conductive impurities are then ion-implanted into the substrate to form source/drain regions. Next, an interlayer insulating layer is formed on the entire surface of the substrate, and a contact electrode connected with the gate line or the source/drain regions is formed in the interlayer insulating layer. Then, a line connected with the contact electrode is formed on the interlayer insulating layer.
The above method is commonly used for manufacturing a memory device such as a dynamic random access memory (DRAM) device, where transistors having the above-described MOS structure are arranged in a matrix form. Referring to FIG. 1, the device includes a contact electrode 30 connected with a gate line 20 and formed in a peripheral circuit region 40. The contact electrode 30 is vertically connected with a power source line for providing a predetermined voltage to the gate line 20 formed in a cell array region 10.
However, as the semiconductor device becomes highly integrated, a memory device having a plurality of gate lines has a limitation in reducing a linewidth of a gate line formed on a surface of a substrate of the memory device. Accordingly, a method is under development to reduce a linewidth of the gate line by forming a secondary gate line of a spacer shape with a thin insulating layer interposed on sidewalls of the gate line on the substrate. Therefore, power supply to the secondary gate line becomes an issue.